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nand2tetris/projects/03/a/RAM64.hdl
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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM64.hdl
/**
* Memory of 64 registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM64 {
IN in[16], load, address[6];
OUT out[16];
PARTS:
DMux8Way(in=load,sel=address[0..2],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h);
RAM8(in=in,load=a,address=address[3..5],out=outa);
RAM8(in=in,load=b,address=address[3..5],out=outb);
RAM8(in=in,load=c,address=address[3..5],out=outc);
RAM8(in=in,load=d,address=address[3..5],out=outd);
RAM8(in=in,load=e,address=address[3..5],out=oute);
RAM8(in=in,load=f,address=address[3..5],out=outf);
RAM8(in=in,load=g,address=address[3..5],out=outg);
RAM8(in=in,load=h,address=address[3..5],out=outh);
Mux8Way16(a=outa,b=outb,c=outc,d=outd,e=oute,f=outf,g=outg,h=outh,sel=address[0..2],out=out);
}