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solutions_only/project 03/RAM4K.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/b/RAM4K.hdl
+
+/**
+ * Memory of 4K registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM4K {
+    IN in[16], load, address[12];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load,sel=address[0..2],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h);
+    RAM512(in=in,load=a,address=address[3..11],out=outa);
+    RAM512(in=in,load=b,address=address[3..11],out=outb);
+    RAM512(in=in,load=c,address=address[3..11],out=outc);
+    RAM512(in=in,load=d,address=address[3..11],out=outd);
+    RAM512(in=in,load=e,address=address[3..11],out=oute);
+    RAM512(in=in,load=f,address=address[3..11],out=outf);
+    RAM512(in=in,load=g,address=address[3..11],out=outg);
+    RAM512(in=in,load=h,address=address[3..11],out=outh);
+    Mux8Way16(a=outa,b=outb,c=outc,d=outd,e=oute,f=outf,g=outg,h=outh,sel=address[0..2],out=out);
+}