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2025-07-16 13:00:37 +03:00
commit 7894b48931
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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/Bit.hdl
+
+/**
+ * 1-bit register:
+ * If load[t] == 1 then out[t+1] = in[t]
+ *                 else out does not change (out[t+1] = out[t])
+ */
+
+CHIP Bit {
+    IN in, load;
+    OUT out;
+
+    PARTS:
+    Mux(a=out2,b=in,sel=load,out=out1);
+    DFF(in=out1,out=out2,out=out);
+}
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+CHIP DMux8Way16 {
+    IN in[16], sel[3];
+    OUT a[16], b[16], c[16], d[16], e[16], f[16], g[16], h[16];
+
+    PARTS:
+	DMux8Way(a=a[0],b=b[0],c=c[0],d=d[0],e=e[0],f=f[0],g=g[0],h=h[0],sel=sel,in=in[0]);
+	DMux8Way(a=a[1],b=b[1],c=c[1],d=d[1],e=e[1],f=f[1],g=g[1],h=h[1],sel=sel,in=in[1]);
+	DMux8Way(a=a[2],b=b[2],c=c[2],d=d[2],e=e[2],f=f[2],g=g[2],h=h[2],sel=sel,in=in[2]);
+	DMux8Way(a=a[3],b=b[3],c=c[3],d=d[3],e=e[3],f=f[3],g=g[3],h=h[3],sel=sel,in=in[3]);
+	DMux8Way(a=a[4],b=b[4],c=c[4],d=d[4],e=e[4],f=f[4],g=g[4],h=h[4],sel=sel,in=in[4]);
+	DMux8Way(a=a[5],b=b[5],c=c[5],d=d[5],e=e[5],f=f[5],g=g[5],h=h[5],sel=sel,in=in[5]);
+	DMux8Way(a=a[6],b=b[6],c=c[6],d=d[6],e=e[6],f=f[6],g=g[6],h=h[6],sel=sel,in=in[6]);
+	DMux8Way(a=a[7],b=b[7],c=c[7],d=d[7],e=e[7],f=f[7],g=g[7],h=h[7],sel=sel,in=in[7]);
+	DMux8Way(a=a[8],b=b[8],c=c[8],d=d[8],e=e[8],f=f[8],g=g[8],h=h[8],sel=sel,in=in[8]);
+	DMux8Way(a=a[9],b=b[9],c=c[9],d=d[9],e=e[9],f=f[9],g=g[9],h=h[9],sel=sel,in=in[9]);
+	DMux8Way(a=a[10],b=b[10],c=c[10],d=d[10],e=e[10],f=f[10],g=g[10],h=h[10],sel=sel,in=in[10]);
+	DMux8Way(a=a[11],b=b[11],c=c[11],d=d[11],e=e[11],f=f[11],g=g[11],h=h[11],sel=sel,in=in[11]);
+	DMux8Way(a=a[12],b=b[12],c=c[12],d=d[12],e=e[12],f=f[12],g=g[12],h=h[12],sel=sel,in=in[12]);
+	DMux8Way(a=a[13],b=b[13],c=c[13],d=d[13],e=e[13],f=f[13],g=g[13],h=h[13],sel=sel,in=in[13]);
+	DMux8Way(a=a[14],b=b[14],c=c[14],d=d[14],e=e[14],f=f[14],g=g[14],h=h[14],sel=sel,in=in[14]);
+	DMux8Way(a=a[15],b=b[15],c=c[15],d=d[15],e=e[15],f=f[15],g=g[15],h=h[15],sel=sel,in=in[15]);
+}
@@ -0,0 +1,44 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/PC.hdl
+
+/**
+ * A 16-bit counter with load and reset control bits.
+ * if      (reset[t] == 1) out[t+1] = 0
+ * else if (load[t] == 1)  out[t+1] = in[t]
+ * else if (inc[t] == 1)   out[t+1] = out[t] + 1  (integer addition)
+ * else                    out[t+1] = out[t]
+ */
+
+CHIP PC {
+    IN in[16],load,inc,reset;
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=true,sel[0]=reset,sel[1]=load,sel[2]=inc,a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h);
+    
+    DFF(in=inc,out=inct);
+    And(a=inc,b=inct,out=out1);
+    Mux16(a=in,b=out4,sel=out1,out=out2);
+    Inc16(in=out2,out=out3);
+    Register(in=out3,load=load,out=out4,out=out);
+    
+    Not(in=a,out=notа);
+    Register(in=in,load=notа,out=outA);
+
+    And16(a[0..15]=false,b[0..15]=false,out=outB);
+    
+    Register(in=in,load=c,out=outC);
+    
+    And16(a[0..15]=false,b[0..15]=false,out=outD);
+    
+
+    And16(a[0..15]=false,b[0..15]=false,out=outF);
+    
+    Register(in=in,load=g,out=outG);
+    
+    And16(a[0..15]=false,b[0..15]=false,out=outH);
+    And16(a[0..15]=false,b[0..15]=false,out=outE);
+    Mux8Way16(a=outA,b=outB,c=outC,d=outD,e=outE,f=outF,g=outG,h=outH,sel[0]=reset,sel[1]=load,sel[2]=inc,out=out67);
+    }
@@ -0,0 +1,24 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/b/RAM16K.hdl
+
+/**
+ * Memory of 16K registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM16K {
+    IN in[16], load, address[14];
+    OUT out[16];
+
+    PARTS:
+    DMux4Way(in=load,sel=address[0..1],a=a,b=b,c=c,d=d);
+    RAM4K(in=in,load=a,address=address[2..13],out=outa);
+    RAM4K(in=in,load=b,address=address[2..13],out=outb);
+    RAM4K(in=in,load=c,address=address[2..13],out=outc);
+    RAM4K(in=in,load=d,address=address[2..13],out=outd);
+    Mux4Way16(a=outa,b=outb,c=outc,d=outd,sel=address[0..1],out=out);
+}
@@ -0,0 +1,28 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/b/RAM4K.hdl
+
+/**
+ * Memory of 4K registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM4K {
+    IN in[16], load, address[12];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load,sel=address[0..2],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h);
+    RAM512(in=in,load=a,address=address[3..11],out=outa);
+    RAM512(in=in,load=b,address=address[3..11],out=outb);
+    RAM512(in=in,load=c,address=address[3..11],out=outc);
+    RAM512(in=in,load=d,address=address[3..11],out=outd);
+    RAM512(in=in,load=e,address=address[3..11],out=oute);
+    RAM512(in=in,load=f,address=address[3..11],out=outf);
+    RAM512(in=in,load=g,address=address[3..11],out=outg);
+    RAM512(in=in,load=h,address=address[3..11],out=outh);
+    Mux8Way16(a=outa,b=outb,c=outc,d=outd,e=oute,f=outf,g=outg,h=outh,sel=address[0..2],out=out);
+}
@@ -0,0 +1,28 @@
+// This file is part of the materials accompanying the book 
+// "The Elements of Computing Systems" by Nisan and Schocken, 
+// MIT Press. Book site: www.idc.ac.il/tecs
+// File name: projects/03/b/RAM512.hdl
+
+/**
+ * Memory of 512 registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM512 {
+    IN in[16], load, address[9];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load,sel=address[0..2],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h);
+    RAM64(in=in,load=a,address=address[3..8],out=outa);
+    RAM64(in=in,load=b,address=address[3..8],out=outb);
+    RAM64(in=in,load=c,address=address[3..8],out=outc);
+    RAM64(in=in,load=d,address=address[3..8],out=outd);
+    RAM64(in=in,load=e,address=address[3..8],out=oute);
+    RAM64(in=in,load=f,address=address[3..8],out=outf);
+    RAM64(in=in,load=g,address=address[3..8],out=outg);
+    RAM64(in=in,load=h,address=address[3..8],out=outh);
+    Mux8Way16(a=outa,b=outb,c=outc,d=outd,e=oute,f=outf,g=outg,h=outh,sel=address[0..2],out=out);
+}
@@ -0,0 +1,28 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/RAM64.hdl
+
+/**
+ * Memory of 64 registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM64 {
+    IN in[16], load, address[6];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load,sel=address[0..2],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h);
+    RAM8(in=in,load=a,address=address[3..5],out=outa);
+    RAM8(in=in,load=b,address=address[3..5],out=outb);
+    RAM8(in=in,load=c,address=address[3..5],out=outc);
+    RAM8(in=in,load=d,address=address[3..5],out=outd);
+    RAM8(in=in,load=e,address=address[3..5],out=oute);
+    RAM8(in=in,load=f,address=address[3..5],out=outf);
+    RAM8(in=in,load=g,address=address[3..5],out=outg);
+    RAM8(in=in,load=h,address=address[3..5],out=outh);
+    Mux8Way16(a=outa,b=outb,c=outc,d=outd,e=oute,f=outf,g=outg,h=outh,sel=address[0..2],out=out);
+}
@@ -0,0 +1,29 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/RAM8.hdl
+
+/**
+ * Memory of 8 registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM8 {
+    IN in[16], load, address[3];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load,sel=address,a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h);
+
+    Register(in=in,load=a,out=outa);
+    Register(in=in,load=b,out=outb);
+    Register(in=in,load=c,out=outc);
+    Register(in=in,load=d,out=outd);
+    Register(in=in,load=e,out=oute);
+    Register(in=in,load=f,out=outf);
+    Register(in=in,load=g,out=outg);
+    Register(in=in,load=h,out=outh);
+    Mux8Way16(a=outa,b=outb,c=outc,d=outd,e=oute,f=outf,g=outg,h=outh,sel=address,out=out);
+}
@@ -0,0 +1,34 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/Register.hdl
+
+/**
+ * 16-bit register:
+ * If load[t] == 1 then out[t+1] = in[t]
+ * else out does not change
+ */
+
+CHIP Register {
+    IN in[16], load;
+    OUT out[16];
+
+    PARTS:
+    Bit(in=in[0],load=load,out=out[0]);
+    Bit(in=in[1],load=load,out=out[1]);
+    Bit(in=in[2],load=load,out=out[2]);
+    Bit(in=in[3],load=load,out=out[3]);
+    Bit(in=in[4],load=load,out=out[4]);
+    Bit(in=in[5],load=load,out=out[5]);
+    Bit(in=in[6],load=load,out=out[6]);
+    Bit(in=in[7],load=load,out=out[7]);
+    Bit(in=in[8],load=load,out=out[8]);
+    Bit(in=in[9],load=load,out=out[9]);
+    Bit(in=in[10],load=load,out=out[10]);
+    Bit(in=in[11],load=load,out=out[11]);
+    Bit(in=in[12],load=load,out=out[12]);
+    Bit(in=in[13],load=load,out=out[13]);
+    Bit(in=in[14],load=load,out=out[14]);
+    Bit(in=in[15],load=load,out=out[15]);
+    
+}